1. Field of the Invention
This invention relates generally to synchronous memory devices, and, more particularly, to a synchronous memory device adapted to receive input data and provide output data synchronized with a common external clock signal.
2. Description of the Related Art
Memory devices, such as synchronous dynamic random access memories (SDRAM) have been widely used to enhance the performance of computer systems executing memory intensive applications. Synchronous memory devices receive and deliver data coincident with a clock signal. In previous SDRAM devices, an external clock signal is received by the device. Input signals and data are received synchronized with the external clock signal. Due to internal delays associated with the components of the memory device, the phase of the external clock signal is shifted within the memory device, such the output data delivered from the device is no longer exactly aligned with the external clock signal. A typical SDRAM can read or write data on the rising edge of a clock cycle. The phase difference between the external clock signal and the data clock signal is less than one clock cycle (e.g., 5 ns), so the output data may be received prior to the next rising edge of the external clock signal.
To increase the bandwidth of memory devices, it has been proposed to receive data and provide output data on both the rising and falling edges of the clock signal. In such an arrangement, the phase delay in the external clock signal produced by the memory device becomes problematic. If output data were to be delivered on both the rising and falling edges in the manner used for present SDRAM devices (i.e., using a delayed data clock signal), the falling edge data is valid during the subsequent rising edge of the external clock signal. Such an arrangement generates timing problems for other devices accessing the memory device.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
One aspect of the present invention is seen in a memory device including a data array, array control logic, a delay locked loop circuit, timing control logic, and a first storage device. The array control logic is adapted to receive a read command synchronized with an external clock signal and to read at least a first data element from the data array based on the read command. The delay locked loop circuit is adapted to receive the external clock signal and delay the external clock signal by a programmable amount to generate a delay locked loop clock signal. The timing control logic is adapted to generate a first input enable signal based on the external clock signal and a first output enable signal based on the delay locked loop clock signal. The first storage device adapted to receive the first data element. The first storage device has an input terminal enabled in response to the first input enable signal and an output terminal enabled in response to the first output enable signal.
Another aspect of the present invention is seen in a method for accessing a memory device. A read command is received synchronized with an external clock signal. A data array is accessed to read at least a first data element from the data array based on the read command. The external clock signal is delayed by a programmable amount to generate a delay locked loop clock signal. A first input enable signal is generated based on the external clock signal and a first output enable signal based on the delay locked loop clock signal. The first data element is stored in a first data storage device in response to the first input enable signal and output from the first data storage device in response to the first output enable signal.